For decades, silicon characterization has been built around Process, Voltage, and Temperature, or PVT. We characterize devices across process variation, sweep voltage and frequency, control temperature, generate SHMOO plots, and establish the operating envelope of the silicon.

That methodology remains fundamental. But today’s high-performance processors are increasingly systems in their own right. An AI accelerator may contain thousands of compute elements, distributed SRAM, high-speed SerDes, PCIe and Ethernet interfaces, multiple clock and power domains, advanced packaging, firmware, operating systems, compilers and application software.

Two devices operating at exactly the same voltage, frequency, and temperature can behave differently depending on what they are being asked to do.

This suggests adding another dimension: PVTW: Process × Voltage × Temperature × Workload

Frequency can be swept within this characterization space to determine operating margin.

The objective is not to replace traditional ATE characterization with System Level Test. It is to combine the electrical precision and control available from ATE with the realistic operating environment available from SLT, while retaining the ability to use either independently.

One way to implement PVTW is through a hybrid characterization architecture integrating ATE resources and SLT capability.

There is no reason to recreate resources that already exist in ATE. Existing ATE infrastructure, including older generation platforms, can provide programmable device power supplies, individual rail control and measurement, variable frequency clocks, digital stimulus and capture, ATPG and structural content, parametric measurements, and conventional SHMOO characterization.

The processor can boot firmware and an operating system, load drivers and runtime software, and execute deterministic workloads designed to exercise specific parts of the architecture.

Source link