AMD’s EPYC ‘Venice’ CPUs are the first to debut the new Zen 6 architecture, and we’ve been testing two chips from the range over the past several weeks to see how they compare to Nvidia’s Vera, and more broadly, how the Zen 6 architecture departs from Zen 5 ahead of the expected consumer-focused Olympic Ridge launch next year. Zen 5 was a ground-up redesign of AMD’s storied Zen core, and Zen 6 takes that foundation and expands it in just about every regard.

Zen 6 uses TSMC’s N2P node, but it also comes with significant architectural changes under the hood. Within the core, a redesigned vector engine pushes AMD’s SIMD performance even higher, and it now natively supports half-precision FP16 instructions alongside full, 32-bit precision. It also splits integer schedulers within the execution engine, allowing for more instructions in flight through the core.

Across the die, AMD made other significant changes. The single IOD of previous generations is now split across two IODs, giving the SP7 platform access to 16 memory channels (though at the cost of PCIe 6.0 lanes compared to the previous generation and SP8 platform).

The CCDs have been upgraded, too, for the first time since Zen 3. A standard Zen 6 CCD can now scale up to 12 cores, while a Zen 6c packs 32 cores. With Zen 5 and 5c, CCDs topped out at eight cores and 16 cores, respectively. For the Zen 6c CCD, AMD also doubled the amount of shared L3 per core, which effectively quadruples the L3 compared to Zen 5c, since the CCD packs twice the number of cores.

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