The rapid pace of change in AI models and approaches is creating confusion over what to test, when to test it, and what to monitor once chips are in the field.

Until recently, test targets and the timing for test insertions generally were determined by fab processes and the laws of physics, and the results of those tests were deterministic and quantifiable. But starting with the rollout of generative AI and the ensuing explosion of data centers, the gap has widened between the rollout of new algorithms and use models and the time it takes to deploy a chip in the field.

An increasing number of high-performance processors used in data centers, and many at the edge, are multi-die assemblies. The chips are more complex and take longer to design, manufacture, package, and assemble, and the workloads for which they are designed often change by the time those chips leave final test. Along the way, there are more test insertions along the way, each of which generates more data.

The tests are more complex and varied, as well. In addition to electrical tests, these chips need to be analyzed for mechanical integrity. AI workloads can stress one part of a multi-die assembly more than others, and they can change quickly as algorithms and use cases evolve. That, in turn, requires increasingly complex multiphysics simulations and more real-time monitoring of processor and memory utilization, thermal gradients, and datapath throughput, along with accelerated aging that can affect signal integrity.

“It’s a huge challenge,” said Scott Segura, vice president of sales at Advantest .

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