Hybrid bonding represents a paradigm shift in advanced packaging, replacing 35 µm off-chip microbumps with 10 µm pitch or smaller pad-to-pad interconnects on-chip. It can be used to join silicon-to-silicon, as in DRAM-DRAM bonding in future HBM devices, or even disparate materials like GaN-on-silicon.

This elegant process, which is available on wafer-to-wafer or die-to-wafer platforms, reduces signal delay to negligible levels while enabling smaller, thinner packages with unmatched memory/processor speeds and bandwidth. It also consumes significantly less power.

Hybrid bonding’s success depends on the performance of advanced bonding equipment, as well as metrology’s ability to verify critical alignment, cleanliness, planarity and surface properties — both before and after bonding. Solving these challenges is proving essential to realizing the vision of true 3D integration at the bonded-chip level.

But as hybrid bonding pitches continue to scale down below today’s production levels of 4 to 9 µm, some inspection and metrology methods are struggling to meet the spatial resolution and sensitivity needed to catch all relevant defect types, especially ones buried at the bond interface. Particles, voids, overlay errors, roughness, CMP defects and warpage threaten the bond quality between chips. Even a single particle can delaminate the top wafer from the one below, resulting in catastrophic failure.

At times, conventional metrology fails to differentiate a killer defect from minor topographical variation. A handful of tools, including non-destructive optical, IR, X-ray, profilometry, AFM, and acoustic inspection tools, are working to resolve critical defects smaller than 100 nm. These are some of the most stringent requirements ever imposed on a semiconductor process.

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