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AMD’s Venice-X maxes out family at 5.3 GHz, returning 3D V-Cache to data center after four years

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AMD’s Venice-X maxes out family at 5.3 GHz, returning 3D V-Cache to data center after four years

AMD missed out on deploying Turin-X CPUs in the previous generation, giving its 3D V-Cache tech a four-year hiatus from the data center following the launch of Genoa-X in 2023. In the second half of next year, 3D V-Cache is coming back for HPC with Venice-X, matching the 96 cores and 1,152 MB of L3 cache available on the EPYC 9684X (Genoa-X), but with vastly higher clock speeds, PCIe 6.0, and nearly four times the per-socket memory bandwidth.

After first bringing hybrid bonding to EPYC processors with Milan-X in 2022, AMD followed up a little over a year later with Genoa-X. Turin came and went without a chip sporting stacked SRAM, but now, it’s back with Venice-X. The critical change this time around doesn’t come from big jumps in core count — and consequently cache — as is the case with the standard SP7 lineup. Rather, it’s the 5.3 GHz boost clock speed, another pillar of Venice broadly, that’s particularly beneficial in the HPC workloads Venice-X targets.

As you can see from the top EPYC -X chips from previous generations, boost clocks were significantly lower for the X chips, and higher frequencies were available within the standard chips from each family. Milan scaled up to 4.1 GHz, while Genoa could climb to 4.4 GHz, just not on the EPYC -X chips. Venice-X brings up to the maximum 5.3 GHz boost clock available across the range, unifying a high frequency with a large pool of bonded L3 for HPC workloads.

There are still details missing about Venice-X, including the base frequency, how many SKUs are in the lineup and what their specs are, and the TDP (though the 400 to 600 W range available to other Venice CPUs is likely).


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