Experts at the Table: Semiconductor Engineering sat down to discuss the growing thermal challenges and trade-offs as dies are stacked, vertically integrated, and harder to cool, with Lang Lin, director of product management at Synopsys; Jack Berg, vice president of business development at Silvaco; Satish Radhakrishnan, head of semiconductor and electronics at Vinci; Chris Mueth, director of new markets management at Keysight EDA; and John Ferguson, senior director of product management at Siemens EDA. What follows are excerpts of that conversation, which was held behind closed doors at the recent Design Automation Conference. To view part one of this discussion, click here. Part two is here.
SE: One of the big trade-offs in advanced designs is voltage versus current. How do you balance that?
Lin : If you reduce the voltage, it will change your timing and reduce the performance. But it also reduces heat. If you keep running the chip fast, you will run into a lot of thermal problems. These are conflicting physics. You need to find the sweet spot for your chip. You need to try the real combination of, say, this voltage versus this timing budget. And you need to do a loop of timing, thermal, and supply voltage or power integrity co-optimization. You have to close this loop and run a couple different workloads to make sure there is not a failure or any other problems. We don’t have a tool yet to do this big loop, so the engineer may be asking how to solve their place-and-route problem while also running timing, thermal, and voltage.
Source link
