The CPO revolution is at our doorstep. But transforming data center interconnects requires overcoming new challenges in architecture, power delivery, mechanical design, and thermal management. Of these, thermal management has emerged as one of the most critical areas for successfully deploying co-packaged optics (CPO) in hyperscale AI environments.

Thermal instability has been a concern for CPO technology. Ayar Labs and Global Unichip Corp. (GUC) jointly conducted thermal co-simulation of the advanced package design and determined the thermal floor map for the package and subsequent chiplets, including air- and liquid-cooled environments.

Since thermal stability has been raised as a concern for micro-ring-based CPO, we want to address it head-on. Our co-simulation data show that CPO can operate reliably within the thermal envelope of advanced multi-chip packages. We’re sharing these results to give hyperscalers the confidence to move forward with CPO deployments at scale.

Let’s start with the new multi-chip package (MCP) design that integrates Ayar Labs’ TeraPHY optical engines into GUC’s advanced packaging and ASIC workflow. The new XPU MCP design replaces traditional electrical interconnects with Ayar Labs’ optical engines, which are attached directly to the MCP organic substrate. This architecture enables a full-duplex optical interface of more than 100 Tbps from the XPU package, an improvement of more than an order of magnitude over current XPUs.

UCIe-S provides bandwidth between the optical engines and the I/O chiplets over the MCP substrate. UCIe-A, on the other hand, is used for communication between the I/O chiplet and the main AI die over local silicon interconnect (LSI) bridges.

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