Every generation of AI and data center silicon brings more logic, more cores, and more scan content that has to reach the device for test. Chiplet-based packages compound it, because each die arrives with its own test requirements and its own patterns. DFT and test engineering teams need better solutions to get content to the device fast enough to keep test time and test cost in line.

One such solution is Siemens’ Tessent Streaming Scan Network, which packetizes scan data so it can be delivered efficiently and shared across cores. Tessent In-System Test builds on this by adding an on-chip controller that accepts deterministic patterns over a standard AXI bus, meaning test content can arrive through a functional interface the device already carries, such as PCIe or USB, rather than through a dedicated test port.

Utilizing this approach with Teradyne UltraFLEXplus results in a combined solution leveraging a programming model test engineers already use. Teradyne has integrated Siemens Tessent Silicon Executable into the UltraPort server and the IG-XL software on UltraFLEXplus. Content generated in the Tessent shell flow is delivered to the device over the device’s own PCIe interface through UltraPort, and the test is set up, executed, and debugged inside the standard IG-XL programming model. Failure data returns in the formats the Tessent diagnosis ecosystem already consumes, so established yield and failure analysis flows carry straight over.

Fig. 2: Tessent Silicon Executable running on the UltraPort Server. Source: Teradyne

Teradyne and Siemens EDA have been building joint solutions since 2000, when built-in self-test first met automatic test equipment.

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