Experts At The Table: The industry is forging a path from single-site to multi-site testing while system architectures and connector types continue to evolve. Semiconductor Engineering sat down with Matt Griffin, senior product manager for optoelectronics test at Teradyne; Ira Leventhal, vice president of research and venture at Advantest America; Dave Armstrong, fellow at ISE Labs, a subsidiary of ASE Group; and Kazuo Yamaguchi, silicon photonics researcher and engineer at Keysight Technologies. What follows are excerpts of that conversation. To view part one, click here.

Fig. 1: (L-R): Teradyne’s Griffin; Keysight’s Yamaguchi; ISE Labs’ Armstrong; Advantest’s Leventhal.

SE: Is it true that you can only test one die at a time today?

Armstrong: I would hope some insertions will go away over time, but right now there are more things being added than being subtracted. It’s a hard one. In terms of testing one die, that depends on the die. If an 8 kW GPU is your main ASIC, and you have multiple connectors around multiple sides of the part from a tester resource standpoint, and the amount of power a tester can deliver and take out of the part, it’s pretty challenging to get beyond one die. But if you look down the NPO-versus-CPO path, NPO is typically a single connector device. You’re going to have to be able to go to multi-site to scale that to high volume. Insertions two and three are the fertile ground for multi-site. Those are longer more complex test insertions.

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