Cadence’s Mick Posner introduces a physical AI sub-project workstream to extend the OCP’s Foundation Chiplet System Architecture’s data center, cloud, and server-centric baseline with the specification requirements to satisfy real-time, safety-critical physical systems, while retaining everything FCSA already defines.

Synopsys’ Charlie Matar considers how design focus is shifting from the server to the rack, with silicon behavior shaping rack-level power and cooling requirements, while rack constraints influence decisions inside chips and packages.

Siemens’ Harry Foster warns that while verification complexity has been managed by dividing large problems into smaller pieces, new challenges are emerging as the number and diversity of interactions influencing correct SoC behavior grows.

Arm’s Zenon (Zhilong) Xiu examines how quarter-tile and structured sparsity outer product instructions make the SME2 programming model better suited to small, dense, quantized, and sparse matrix workloads in modern AI software.

Keysight’s Linas Dauksa digs into AI data center infrastructure, including key components, energy demands and power density challenges, the array of liquid cooling technologies available, and what differentiates hyperscale facilities.

SEMI’s Sungho Yoon considers factors related to a forecasted increase in wafer shipments, including rising process material sales and a high number of new and upcoming production lines.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Technology editor Brian Bailey poses the age-old question for anyone involved in the verification of semiconductor systems: in the age of AI, who verifies the verifier?

Axiomise’s Vidya Chandran Darbari and Ashish Darbari dig into what biological reasoning can teach us about verifying silicon systems.

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