A top-down semiconductor development flow has long been a goal for chip design, and shift left is certainly making that increasingly possible. The problem is that the starting point — the specification — is often incomplete or nonexistent, because the chip industry has been notoriously bad at writing specifications.

There are several ways to insert AI into existing flows. But just because something can be done doesn’t mean it should be. This is one of the big challenges facing AI adoption. Many existing tasks could be done more efficiently using an agentic flow, but it’s not clear whether that is the right thing to do.

This limitation becomes especially apparent when AI starts to help with something that has been woefully inadequate in the past — the creation of good, complete specifications. The big question is whether AI can enable designs, or verification environments, to be automatically derived from a specification. Perhaps a more correct goal is whether AI can help create better specifications. With better specifications, downstream design becomes a lot easier.

“AI can generate a SystemVerilog assertion in seconds,” says Ben Cohen, verification technologist and book author. “Whether that assertion means anything depends entirely on what it was generated from, and in practice that source is rarely a single, clean, natural-language specification. It is just as often an ambiguous paragraph that needs clarifying before it can be trusted.”

Solving this problem should be considered a high priority. “The increasing complexity of modern SoC designs is making AI-assisted artefact generation and verification closure a practical requirement rather than a research option,” says Simon Davidmann, AI and EDA researcher at the University of Southampton.

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