The semiconductor industry is rapidly transitioning from monolithic SoCs to chiplet-based architectures. At the same time, AI workloads are evolving beyond cloud inference into physical AI: systems that perceive, reason, and act in the real world. Autonomous vehicles, industrial robots, humanoid robots, drones, and intelligent manufacturing systems all require continuous, high-volume data flow between heterogeneous compute engines.

However, these two trends expose a weakness in today’s die-to-die communication architectures. While coherent interconnect protocols have been highly successful for processor-centric systems, they are fundamentally mismatched to the traffic patterns generated by modern AI accelerators.

As a result, a new approach is needed that involves transporting the native packetized traffic of the NoC directly across die boundaries using a stable, invariant interface.

Traditional processors are dominated by memory accesses, synchronization, and cache coherence. Physical AI systems are different. A modern automotive compute platform may simultaneously execute:

Rather than exchanging individual cache lines, these engines often exchange continuous streams of feature maps, tensors, point clouds, video frames, and intermediate inference results. These data streams often consist of hundreds of kilobytes, or even megabytes, moving between specialized accelerators at deterministic rates. The communication pattern resembles a high-performance dataflow network more than a coherent symmetric multi-processor system. As physical AI systems become more capable, the amount of accelerator-to-accelerator traffic continues to grow faster than CPU-to-memory traffic.

Coherent die-to-die protocols remain the right solution for many applications and perform exceptionally well for:

These protocols were designed to maintain memory consistency while moving relatively small cache-line-sized transactions.

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