AMD's Vitis Hardware in the Loop enables system-level validation on Versal silicon directly from MATLAB or Python, enhancing verification speed and fidelity.

AMD has unveiled its Vitis Hardware in the Loop (Vitis HIL) solution, designed to enhance system-level validation for its Versal adaptive SoCs and FPGAs directly from MATLAB or Python environments. This approach aims to bridge the gap between simulation and hardware testing, leveraging real silicon for faster and more precise verification. The announcement was made in a blog post by Udayan Sinha, published on October 7, 2026.

Vitis HIL integrates existing MATLAB and Python test environments with the validation process for AMD Versal systems, which combine AI engines, programmable logic, and embedded processing. This allows engineering teams to reuse familiar testbenches, stimulus generation, and analysis workflows, saving time and resources compared to rebuilding tools for hardware-specific testing.

The solution supports evaluation on physical silicon using development kits like the Versal AI Core VCK190 and Versal AI Edge VEK280. These kits target applications ranging from aerospace signal processing to automotive and industrial edge workloads. By running designs on actual hardware, Vitis HIL captures real-world pipeline latency, fixed-point rounding, and memory effects that simulation alone may not reveal. According to AMD, this capability is particularly valuable for validating complex designs such as DSP algorithms and AI Engine computations that require deterministic performance and spectral fidelity.

Vitis HIL's workflow is split into two phases. An initial setup phase configures the hardware and generates a bootable image, while an iterative test phase enables repeated validation as the design evolves.

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