OpenAI and Synopsys have signed a multi-year agreement to jointly develop GPT-Synopsys, a specialized model optimized for semiconductor design using Synopsys's electronic design automation (EDA) tools. According to the September 30 announcement, the partnership “brings together OpenAI's advanced AI capabilities with Synopsys's industry-leading EDA tools and agentic AI capabilities to revolutionize the design of semiconductors.”

Engineers would delegate to agents that run the tools and execute the required processes until the work is ready for review. The companies say this would allow design teams to evaluate more options and deliver more sophisticated chips. Under the preferred partner agreement, OpenAI is licensing Synopsys's tools to develop the model — which will run on OpenAI-hosted infrastructure — after which the companies will jointly release the product and share revenue. The announcement did not disclose a release date or a pricing structure.

Engineers use EDA tools to design and verify chips before manufacturing. This multi-step process begins with writing the hardware description in register-transfer level (RTL) code and using synthesis software to convert it into logic gates. Next, physical design tools lay out the circuit elements and route the connections between them. Lastly, designers close timing, verify functionality, and ensure manufacturing compliance before tapeout for fabrication.

Each of these stages requires several iterations — repeatedly running various tools and troubleshooting issues — to balance critical trade-offs: power, performance, and silicon area (PPA). Synopsys, Cadence, and Siemens EDA have dominated this market for these tools long before the current AI boom. Given the technology's capabilities, it is only natural that AI has found its way into the chip design process , creating a sort of “silicon designing silicon” loop.

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