AMD has revealed a substantial amount of detail on its next-gen Zen 6 CPU architecture, in the form of a technical deep dive on its newly-unveiled EPYC "Venice" range of server chips.

These models will find themselves buried deep within data centers, but the Zen 6 architecture itself looks extremely promising for next-gen Ryzen desktop processors—and quite possibly, your next gaming CPU.

Current Zen 5 CCDs with full-fat performance cores max out at eight cores per chiplet, but a single Zen 6 CCD, based on TSMC’s cutting-edge N2P node, is stuffed with 12 of the beasties—alongside 4 MB of L3 cache per core, the same as Zen 5. That adds up to a total of 48 MB of L3 cache per CCD, as opposed to the 32 MB you'd find on an 8-core Zen 5 chip (via Techpowerup).

A current gen Zen 5 CPU with more than eight cores has to spread them across two CCDs, which can result in latency as the two communicate with each other during multi-threaded tasks. With the upped core count per CCD, a 12-core Zen 6 chip would face no such performance penalty.

It's the "c" core counts that have received the biggest jump in density, though. These aren't the same as Intel's Efficiency cores, instead amounting to scaled down performance cores designed to take up less die space and spread the workload during heavily multi-threaded tasks.

In the case of Zen 6c, 32 cores can be squeezed onto a single core complex, double that of a Zen 5 equivalent.

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