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Wafer-Scale Sub-5nm Channel Monolayer MoS2 Transistors (CMU, UF, MIT et al.)

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Wafer-Scale Sub-5nm Channel Monolayer MoS2 Transistors (CMU, UF, MIT et al.)

Researchers at Carnegie Mellon University, University of Florida, MIT, Texas A&M University et al. published a technical paper titled “Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit.”

“Here, we report monolayer MoS₂ transistors with physical channel lengths below 5 nm, achieving a subthreshold swing of 88 mV/dec and an on/off ratio above 106. These results surpass both the theoretical subthreshold limit of silicon and state-of-the-art emerging semiconductors-based transistors at comparable dimensions. To ensure high throughput, we develop a photolithography based, complementary metal oxide semiconductor (CMOS) compatible process and demonstrate 4-inch wafer-scale integration.”

Lin, S., T. Huang, N. Yang, et al. “Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit.” Nature Communications (September 2026). https://doi.org/10.1038/s41467-026-77186-9.  Open Access.

The post Wafer-Scale Sub-5nm Channel Monolayer MoS2 Transistors (CMU, UF, MIT et al.) appeared first on Semiconductor Engineering.



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