Experts At The Table: Demand for parallelism and power efficiency is shifting chip design from general computing to AI, increasing the need for flexible, modular, and open hardware. This trend is bringing RISC-V into AI acceleration. Customizable hardware can implement AI computations directly instead of relying on fixed CPU designs. Semiconductor Engineering sat down to discuss these issues with Steve Roddy, chief marketing officer at Quadric; Francisca Tan, director of product management and product engineering for Tessent at Siemens EDA; Ewald Liess, senior vice president of sales and business development at SignatureIP; and Dave Kelf, CEO of Breker. What follows are excerpts of that conversation.

SE: With AI models evolving rapidly, architects use RISC-V to design highly specialized extensions. From an IP provider standpoint, how would you balance delivering a standardized, reusable IP core with the extreme customization that customers are demanding for AI workloads?

Leiss : We don’t think that we need to configure because we provide NoC and PCI Express and CXL CHI AMBA interfaces. Based on this, we don’t need to customize. Instead, it’s the NoC that will be configured. Because we have a pre-verified NoC, we can do that with our tools. We can configure customized RISC-Vs. Of course, the customers may modify the RISC-V core with new instructions, but they will stick to the interfaces like the AMBA bus, or CXL, PCI Express interfaces, because this enables them to access the external components that they need, like memory or going off-chip. And this is where we come in.

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