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Randomized Caches in HW: Overheads And Limitations (RUB, Max Planck, Georgia Tech)

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Randomized Caches in HW: Overheads And Limitations (RUB, Max Planck, Georgia Tech)

Researchers at Ruhr University Bochum, the Max Planck Institute for Security and Privacy, and Georgia Tech published “Randomized Caches in Hardware: Challenges and Trade-offs.”

Abstract Excerpt:
“Randomized caches protect against side-channel attacks by obfuscating the mapping of memory addresses to cache locations. Existing proposals typically describe architectural behavior, leaving practical hardware implementation challenges largely unexplored. We implement four prominent designs, CEASER-S, ScatterCache, SassCache, and MIRAGE, and integrate them as the last-level cache (LLC) of a multi-core out-of-order RISC-V system-on-chip (SoC). We identify common and design-specific implementation challenges and develop practical solutions. We evaluate complete FPGA implementations by running SPEC CPU 2017 rate and GAPBS workloads to completion, providing, to our knowledge, the first comparative evaluation of these designs on a common full-system hardware platform.”

Wang, Xinrui, Pascal Kosak, Christof Paar, Daniel Genkin, Yuval Yarom, and Anirban Chakraborty. “Randomized Caches in Hardware: Challenges and Trade-offs.” arXiv preprint arXiv:2611.00282 (2026). CC BY 4.0 license.



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