Experts At The Table: Semiconductor Engineering sat down to discuss recent developments and challenges when using agentic AI for chip design, with Matt Graham, senior group director of verification software product management at Cadence; Harrison Balistreri, head of business development and strategic partnerships at ChipAgents; Alexander Petr, senior director and portfolio manager at Keysight EDA; Sathish Balasubramanian, head of product for EDA AI at Siemens EDA; and Anand Thiruvengadam, executive director and head of AI product management at Synopsys. This roundtable was held behind closed doors at the recent Design Automation Conference. What follows are excerpts of that discussion. This is the third part of a three-part series. Part one is here. Part two is here. 

L-R: Synopsys’ Thiruvengadam; Keysight’s Petr; Cadence’s Graham; ChipAgents’ Balistreri; and Siemens’ Balasubramanian. 

SE:  Many agentic flows involve a mixture of experts (MoE) or a hierarchy of multi-agents with some type of leader at the top. What developments are you seeing there? Is it a top-down, military-style organization with various security and access clearances, or more of a horizontal team? 

Graham: It is becoming much flatter than an army. If you’d asked me a year ago, I might have said, yes, it is a big hierarchy of agents. There will be mini agents, sub agents, and low agents. There will be generals and lieutenants and whatever else, all the way up. But AI in general, not just EDA, we are migrating much more toward a flat set of skills, or capabilities, or features, or knowledge, or whatever the word is you want to use to describe it.

Source link