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A breakthrough has been made toward overcoming both the speed and endurance limitations of low-power memory. A research team led by professor Min Hyuk Park of the Department of Materials Science and Engineering at Seoul National University College of Engineering has developed a ferroelectric capacitor that operates rapidly at a voltage as low as 0.6 V and can still distinguish between information states without electrical breakdown after 1 trillion switching cycles.

The achievement is significant because it offers a solution to a longstanding challenge in ferroelectric memory: the difficulty of achieving both fast operation and long device lifetime. By precisely engineering the interface between the electrode and the ferroelectric material, the researchers simultaneously achieved a low operating voltage, rapid polarization switching and high cycling stability. Based on these results, they also demonstrated the potential for the technology to be used in next-generation low-power memory with a structure similar to DRAM.

The research was conducted jointly with researchers from Hanyang University, Pohang Accelerator Laboratory and Samsung Electronics, and the findings were published in the journal Nature Communications.

As the volume of data processed by AI servers and mobile devices continues to grow, technologies that can simultaneously improve memory performance and power efficiency are becoming increasingly important. Power efficiency is a particularly critical challenge in both high-bandwidth memory (HBM) used in AI servers and LPDDR, a low-power DRAM standard used in smartphones and other mobile devices.

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