As their dimensions continue to shrink, conventional gate-all-around (GAA) nanosheet transistors may face growing challenges, such as leakage, mobility, resistance, and manufacturing variability.

A proposed self-aligned complementary field-effect transistor (SA-CFET) architecture addresses these constraints by vertically stacking N-channel metal-oxide-semiconductor (NMOS) and P-channel metal-oxide-semiconductor (PMOS) devices and using self-aligned modules to improve density and manufacturability.

A complementary field-effect transistor (CFET) is a transistor architecture that vertically stacks NMOS and PMOS devices. This configuration can reduce cell area, increase effective channel width, and improve electrostatic control compared with side-by-side device layouts.

With SEMulator3D, the Semiverse Solutions team used digital twin process modeling to show that the self-aligned architecture can support static random-access memory (SRAM) and logic cells while delivering a 0.0094 μm² SRAM bit cell, a 52.7% area reduction compared with N3 technology, and at least a 10 nm overlay window across critical contact layers.

Many experts believe that the currently most-advanced transistor architecture, silicon GAA nanosheets, may begin to have physics and manufacturing issues past the 10 angstrom (Å) node. These challenges include:

With these challenges, it is becoming increasingly difficult to scale down the nanosheet device area or enhance device density by simply shrinking the active area, gate, or metal patterning pitch.

CFET architecture stacks PMOS and NMOS vertically to achieve significant area reduction, enhanced performance through larger effective channel width, and improved electrostatics. 1,2,3,4 However, CFET architecture faces its own critical integration challenges: metal gate isolation complexity and contact crowding that can cause electrical shorts or open circuits.

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