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Chip Industry Week In Review

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Chip Industry Week In Review


Fig. 1: Schematic of accelerator archipelago vs. converged GPU. Source: Imagination Technologies

At the TSMC 2026 North America OIP Ecosystem Forum in Santa Clara, several ecosystem partners announced expanded collaborations:

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WashU researchers and collaborators demonstrated heterogeneous photonic integration of single-crystalline nanomembranes on silicon and silicon nitride.

A LANL/University of Pisa-led team reviewed how self-organizing networks of nanowires and nanoparticles adapt their electrical connections to process information and learn directly in HW. The approach could complement conventional computing by enabling energy-efficient, local AI in robots, autonomous vehicles and satellites. “We’re asking what becomes possible when the hardware itself is adaptive,” said co-author Adam Stieg of UCLA, pointing to AI that can operate and adapt locally.

Keysight is supporting UC Berkeley research on new over-the-air test methods for increasingly complex 6G devices and systems.

Moving Test Data Faster: Options and workarounds for improving reliability in chips.

Increasingly complex chip designs require more test data than those developed at older nodes and on single planar dies. The challenge is moving all of that data through the system without slowing down the testing processes. Siemens EDA’s Vidya Neerkundar discusses the different test options, which ones work best where, and how different standards impact the test process.

U. of Pavia, CEA-Leti and ST researchers developed a fully integrated quantum frequency processor on a silicon chip , combining quantum-state generation, frequency mixing, and programmable spectral control on a single silicon-photonics platform.


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