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As transistors inside microchips continue to shrink, the metal wiring that connects them is becoming a growing obstacle to faster, more energy-efficient chips. Narrower wires have greater electrical resistance, while smaller gaps between them increase interference between adjacent signals. These effects impede data transfer and raise energy consumption—an issue known as an interconnect bottleneck, which is especially acute in data-hungry artificial intelligence processors.

A team from the National University of Singapore (NUS), led by Barbaros Oezyilmaz, a professor in the Department of Materials Science and Engineering at the College of Design and Engineering who also holds a joint appointment in the Department of Physics at the Faculty of Science, has developed an atom-thin film of amorphous carbon that could help ease this bottleneck.

The film maintained a dielectric constant, or k-value, of 1.35 at thicknesses down to just 0.8 nanometers. It also withstood strong electric fields and prevented copper ions from passing through it.

"This is a materials bottleneck more than 20 years old: While transistor technology has changed radically, the basic copper-interconnect platform has remained largely intact and is now one of the dominant obstacles to converting further scaling into real performance and energy gains," said Oezyilmaz.

Current chip designs use separate materials to insulate copper wires and keep the copper from spreading into the surrounding insulation. Combining both functions in one film could leave more room for wider copper lines, which have lower resistance and could help move data faster while consuming less energy.

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